1. Field of the Invention
The present invention relates to a transceiver, and more particularly, to a transceiver for a full duplex communication system.
2. Description of the Prior Art
As technology advances, network applications have become more and more popular. FIG. 1 depicts a simplified schematic diagram of a conventional transceiver 100 in a channel of a fast Ethernet device. The transceiver 100 comprises a hybrid circuit 115, which is a three-end device. The transceiver 100 transmits a transmission signal Tx to the channel 110 via the hybrid circuit 115. A receive signal Rx transmitted from the other end of the channel 110 mixes with the signal Tx to form a signal Rx+Tx. The hybrid circuit 115 comprises an echo canceller 130 for removing the components of the signal Tx from the signal Rx+Tx in the channel 110 in order to obtain the receive signal Rx. The transceiver 100 further comprises an analog front-end (AFE) circuit 140 coupled to the hybrid circuit 115 for receiving and processing the receive signal Rx. In practical applications, the hybrid circuit 115 further comprises a digital to analog converter (DAC) 120.
However, an unavoidable parasitic capacitance effect in practical implementations is disregarded and therefore the echo effect of the transceiver 100 cannot be effectively reduced. Additionally, the open-loop output impedance of the hybrid circuit 115 is a finite resistance Ra and the input impedance of the AFE circuit 140 is a finite resistance Rb. Accordingly, the signal insertion loss is Ra/(Ra+Rb) and the equivalent output impedance of the stage prior to the AFE circuit 140 is Ra//Rb. The signal-to-noise ratio (SNR) of the receive signal Rx is thereby reduced. Therefore, the conventional transceiver 100 includes a unit gain buffer 170 prior to the AFE circuit 140 to provide a large input impedance and a tiny output impedance in order to drive the next stage, i.e., the AFE circuit 140, and to prevent any signal from passing back from the AFE circuit 140 to the hybrid circuit 115.
Furthermore, in order to increase the working frequency of the sample and hold circuit 160, the conventional transceiver 100 also includes a unit gain buffer 180 between the AFE circuit 140 and a sample and hold circuit 160 to provide a small output impedance to reduce the equivalent resistance of the RC network.
The transceiver of the prior art utilizes unit gain buffers to drive next stages and this results in increased complexity and cost of the circuit, and the noise level and harmonic distortion of the active elements within are raised. Hence the signal quality decreases.